Recuerda que en las ciencias cualquier problema casi siempere puede tener varias resoluciones, así que aquí compartiremos lo más óptimo y eficiente.
Ejemplo: el cambio universal registra el código verilog
1. Write a Verilog Code for a 4 – bit Universal shift register.
a. Design Code :-
// I hope this will be fairly easy to understand for the reader. It seems like a long code, but that is because of the case statements, otherwise behavioral modelling makes this very, very easy.
`timescale 1ns / 1ps
module universal_shift_register(select, parallelin, left, right, parallelout, clk);
input [1:0] select;
input [3:0] parallelin;
input left;
input right;
input clk;
output [3:0] parallelout;
reg [3:0] parallelout;
always @(posedge clk)
begin
case(select)
2'b00:
begin
parallelout[0] <= parallelout[0];
parallelout[1] <= parallelout[1];
parallelout[2] <= parallelout[2];
parallelout[3] <= parallelout[3];
end
2'b10:
begin
parallelout[0] <= left;
parallelout[1] <= parallelout[0];
parallelout[2] <= parallelout[1];
parallelout[3] <= parallelout[2];
end
2'b01:
begin
parallelout[0] <= parallelout[1];
parallelout[1] <= parallelout[2];
parallelout[2] <= parallelout[3];
parallelout[3] <= right;
end
2'b11:
begin
parallelout[0] <= parallelin[0];
parallelout[1] <= parallelin[1];
parallelout[2] <= parallelin[2];
parallelout[3] <= parallelin[3];
end
endcase
end
endmodule
b. Test Bench Code
`timescale 1ns / 1ps
module testbench();
reg [1:0] selectlines;
reg [3:0] parallelload;
reg leftenter;
reg rightenter;
reg clk = 1'b1;
integer i;
wire [3:0] outputone;
universal_shift_register u1(selectlines, parallelload, leftenter, rightenter, outputone, clk);
always #1 clk = ~clk;
initial
begin
selectlines[0] = 1'b1;
selectlines[1] = 1'b1;
parallelload[0] = 1'b0;
parallelload[1] = 1'b1;
parallelload[2] = 1'b1;
parallelload[3] = 1'b0;
end
initial begin
$display("Value being loaded");
#10
for(i = 3; i >= 0; i = i - 1)
begin
$write("%b", outputone[i]);
end
#10
selectlines[0] = 1'b0;
selectlines[1] = 1'b1;
leftenter = 1'b1;
rightenter = 1'b0;
#2
$display(" ");
$display("After left shift");
for(i = 3; i >= 0; i = i - 1)
begin
$write("%b", outputone[i]);
end
selectlines[0] = 1'b1;
selectlines[1] = 1'b0;
leftenter = 1'b1;
rightenter = 1'b1;
#2
$display(" ");
$display("After right shift");
for(i = 3; i >= 0; i = i - 1)
begin
$write("%b", outputone[i]);
end
selectlines[0] = 1'b0;
selectlines[1] = 1'b0;
leftenter = 1'b1;
rightenter = 1'b0;
#2
$display(" ");
$display("Value being retained");
for(i = 3; i >= 0; i = i - 1)
begin
$write("%b", outputone[i]);
end
end
endmodule
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